Yoshitaka Tsunekawa
Papers
2
Total Citations
4
H-Index
2
About
Yoshitaka Tsunekawa is a researcher in digital arithmetic and VLSI design, with a primary focus on high-speed division circuits for real-time applications. His major contributions center on the development of a high-speed cellular array divider that incorporates a selection function, based on the non-restoring algorithm. This design is capable of handling both fixed-point and floating-point operations, addressing the critical need for fast dividers in digital signal processing and robot control. Despite the niche nature of his work, his key papers—published in 1997 and 1998—have each garnered 2 citations, reflecting their foundational role in specialized hardware design. Tsunekawa’s research bridges the gap between algorithmic efficiency and practical VLSI implementation, offering a solution that balances speed and area constraints. His work is notable for its emphasis on real-time performance, a crucial requirement in embedded systems and robotics. For students and researchers exploring arithmetic unit design, Tsunekawa’s contributions provide a clear example of how theoretical algorithms can be translated into efficient, application-specific hardware.
Research Focus
Key Achievements
Top Papers
- 1
- 2