Datapath

Fully pipelined FPGA-based architecture for real-time SIFT extraction

John Vourvoulakis, John Kalomiros, J.N. Lygouras

Citations: 34 • 2015

Robot fault-tolerance using an embryonic array

A.H. Jackson, R.O. Canham, Andy M. Tyrrell

Citations: 17 • 2003

Design and Implementation of a 64-bit RISC Processor Using VHDL

Rohit Sharma, Vivek Kumar Sehgal, Nitin Nitin, Pranav Bhasker, VERMA ISHITA

Citations: 15 • 2009

Hardware event-driven simulation engine for spiking neural networks

Rodrigo Agís, Eduardo Ros, Javier Díaz, Richard R. Carrillo, Eva M. Ortigosa

Citations: 14 • 2007

Precomputation‐based radix‐4 CORDIC for approximate rotations and Hough transform

Yashrajsinh Parmar, K. Sridharan

Citations: 13 • 2018

DPU-v2: Energy-efficient execution of irregular directed acyclic graphs

Nimish Shah, Wannes Meert, Marian Verhelst

Citations: 10 • 2022

A Novel Processor for Artificial Intelligence Acceleration

Atanas Kostadinov, Guennadi A. Kouzaev

Citations: 6 • 2022

ACHILLES: Accuracy-Aware High-Level Synthesis Considering Online Quality Management

Shayan Tabatabaei Nikkhah, Mahdi Zahedi, Mehdi Kamal, Ali Afzali‐Kusha, Massoud Pedram

Citations: 5 • 2018

Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA

Carlo Sau, Tiziana Fanni, Claudio Rubattu, Luca Fanni, Luigi Raffo, Francesca Palumbo

Citations: 4 • 2020

A multi-resolution approach for massively-parallel hardware-friendly optical flow estimation

Francisco Barranco, Javier Díaz, B. Pino, Eduardo Ros

Citations: 4 • 2012

A strategy for design space exploration

Smita Bakshi, Daniel D. Gajski

Citations: 3 • 1993

Synthesis of Datapath Architectures

Jan M. Rabaey, Chi-min Chu, Phu Hoang, Miodrag Potkonjak

Citations: 3 • 1992

A Symbolic Approach for Checking Functional and Timing Compatibility of Synthesized Designs

Chili-Tung Chen, Alice C. Parker

Citations: 2 • 1993