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About

Wannes Meert is a researcher working at the intersection of probabilistic machine learning, hardware architecture, and embedded computing systems. His work focuses on enabling efficient execution of complex computational models — particularly irregular directed acyclic graphs (DAGs) — on specialized hardware platforms, bridging the gap between algorithmic sophistication and real-world deployment constraints. Among his most notable contributions is the development of the DPU (DAG Processing Unit) and its successor DPU-v2, purpose-built processors designed to handle the irregular data dependencies that challenge conventional CPUs and GPUs in applications ranging from probabilistic inference to robotic navigation. His work on the PIU processor, achieving 248 GOPS/W efficiency using precision-scalable posit arithmetic, demonstrates a commitment to energy-efficient intelligent computing. These innovations collectively address a critical need: making probabilistic and explainable AI models viable on resource-constrained devices. Meert has also contributed to dynamic sensor-frontend optimization for embedded classification, reflecting a broader interest in always-on, low-power sensing systems for human activity recognition. His parallelization framework GraphOpt further extends this vision by tackling scheduling challenges in sparse graph execution. With citations spanning hardware, machine learning, and systems research, Meert's work has meaningful reach across multiple disciplines.