Shirui Zhao
Papers
2
Total Citations
31
H-Index
2
About
Shirui Zhao is a leading computer architect whose research focuses on energy-efficient hardware acceleration for irregular, probabilistic, and graph-based computation. Her major contributions center on designing specialized processors that overcome the limitations of general-purpose CPUs when handling irregular data dependencies in applications like probabilistic machine learning, sparse linear algebra, and robotic navigation. Zhao’s groundbreaking work includes the DPU (DAG Processing Unit), a 28nm chip that leverages precision-scalable posit arithmetic to efficiently process irregular directed acyclic graphs, and the PIU (Probabilistic Inference Unit), a stream-based processor achieving an impressive 248 GOPS/W for probabilistic inference networks. These innovations directly address the growing need for explainable AI and domain-aware computation, offering alternatives to deep neural networks that require less training data. With her most-cited papers accumulating 19 and 12 citations respectively, Zhao’s work is gaining recognition for pushing the boundaries of domain-specific architectures. Her designs demonstrate how custom hardware can unlock new capabilities in probabilistic computing while maintaining remarkable energy efficiency, making her a rising figure in the field of specialized processor design.
Research Focus
Key Achievements
Top Papers
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- 2