A scalable real-time image processing pipeline

Abstract

To speed up image processing in the field of robot vision and industrial inspection, a pipeline element was made which is able to perform fast cellular logic operations. This Cellular Logic Processing Element (CLPE) is able to process binary images with a speed of 100 ns per pixel. The processing element is a CMOS VLSI-device which includes a Writable Logic Array for the storage of sets of 3*3 structuring elements which define the cellular logic operations. This paper describes how such CLPEs can be used for building a pipeline for mixed grey value processing and cellular logic processing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>