Implementation of Folding Architecture Neural Networks into an FPGA for an Optimized Inverse Kinematics Solution of a Six-Legged Robot

Abstract

Solving joint angles for robotic arms using inverse kinematics may involve solving inverse trigonometric equations.Hence it is not always easy to implement such methods using hardware as they have a limited amount of memory. When it comes to robots with many legs the problem becomes more and more complicated. Hence in this paper we focus on 1) the optimization using neural networks, of the truncated power series for the inverse kinematics solution for a six-legged robot, 2) the designing of novel architectural solution using folding technique as means for implementing the neural networks. The inverse solutions were used to approximate the displacement angle for input values for the three servos S1, S2, and S3 used in the robotic arm using the three desired parameters R, Z, and angle θ. The truncated solution was complex and mathematically tedious, requiring 16 coefficients to be used to compute S1 and 165 coefficients to compute S2 and 145 for S3. In this research, Back propagation neural network was used to replace the highly complex power expansions. Single neural networks were used to compute S1, S2, and S3 separately. The networks were optimised such that each network had eight hidden layers. The neural networks provided good accuracy in the solutions obtained. Most importantly, the approach reduced the high demand for mathematical resources significantly below the resources required by the power series method. The work then proceeded with devising an optimised way of implementing the neural networks using hardware. A fully parallel architecture is first proposed and investigated. This approach provides high speed operation however due to the nature of its highly parallel computation; it tends to consume the available digital resources of any targeted embedded system. Folding design was then introduced. It is shownthat the folding design has provided a solution for optimizing digital resources. Using the folding method we found out that it reduces the consumption of digital multipliers by 40%. Then our goal is to implement the folding design into a Virtex-II 2XCV3000 FPGA.