Three-dimensional integrated circuit
Related papers: 2
Top Researchers
Top Cited Papers
New chip-to-wafer 3D integration technology using hybrid self-assembly and electrostatic temporary bonding
Takafumi Fukushima, H. Hashiguchi, J. C. Bea, Yuki Ohara, M. Murugesan, K.-W. Lee, Tetsu Tanaka, Mitsumasa Koyanagi
Citations: 26 • 2012
The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors
Seung-Ho Ok, Yong–Hwan Lee, Jae Woong Shim, Sung Kyu Lim, Byungin Moon
Citations: 2 • 2017