Adder

Universal computing by DNA origami robots in a living animal

Yaniv Amir, Eldad Ben-Ishay, Daniel Levner, Shmulik Ittah, Almogit Abu-Horowitz, Ido Bachelet

Citations: 374 • 2014

Improved parallel matrix multiplication using Strassen and Urdhvatiryagbhyam method

Y. R. Annie Bessant, J. Grace Jency, K. Martin Sagayam, A. Amir Anton Jone, Digvijay Pandey, Binay Kumar Pandey

Citations: 62 • 2023

Dynamic MAC-based architecture of artificial neural networks suitable for hardware implementation on FPGAs

Nadia Nedjah, Richard Marins da Silva, Luiza de Macedo Mourelle, M.V.C. da Silva

Citations: 44 • 2009

A systolic architecture for computation of the manipulator inertia matrix

Masoud Amin-Javaheri, David E. Orin

Citations: 30 • 2005

Real-time DKS on a single chip

Steven S. Leung, M.A. Shanblatt

Citations: 25 • 1987

Series or parallel toehold-mediated strand displacement and its application in circular RNA detection and logic gates

Shulian Bai, Bangtian Xu, Jiangling Wu, Guoming Xie

Citations: 15 • 2023

Approximate FPGA Implementation of CORDIC for Tactile Data Processing Using Speculative Adders

Marta Franceschi, Vincent Camus, Alì Ibrahim, Christian Enz, Maurizio Valle

Citations: 14 • 2017

A new scalable parallel adder based on spiking neural P systems, dendritic behavior, rules on the synapses and astrocyte-like control to compute multiple signed numbers

Thania Frias, Giovanny Sánchez, Luis Garcia, Marco Abarca, Carlos Díaz, Gabriel Sanchez-Perez, Hector Perez‐Meana

Citations: 14 • 2018

RICO: A low power repetitive iteration CORDIC for DSP applications in portable devices

Neha K. Nawandar, Bharat Garg, G. K. Sharma

Citations: 14 • 2016

Analog DNA computing devices toward the control of molecular robots

Satoshi Kobayashi, Kazuya Yanagibashi, Ken Komiya, Kenzo Fujimoto, Masami Hagiya

Citations: 14 • 2014

Reconfigurable parallel VLSI processor for dynamic control of intelligent robots

Yoshichika Fujioka, Michitaka Kameyama, Nobuhiro Tomabechi

Citations: 11 • 1996

Analysis of effects of using exponent adders in IEEE-754 multiplier by VHDL

Ragini Parte, Jitendra Kumar Jain

Citations: 9 • 2015

Residue arithmetic based multiple-valued VLSI image processor

M. Honda, Michitaka Kameyama, T. Higuchi

Citations: 8 • 2003

An Energy Efficient High-Performance CMOS Transmission Gate Full Adder Circuit

Chippe Keerthi, K. Lokesh Krishna, Allabaksh Shaik, Bollu Sireesha, Bodipati Tharun Naidu, Dhandu Venkat Karthik Reddy

Citations: 7 • 2023

Flexible, Light-Interacting, B-Shaped Structures for Computations

Nan Yang, Huaxian Wei, Yubo Zhang

Citations: 6 • 2023

Error injection analysis for triple modular and penta-modular redundancies

Ryo Terada, Minoru Watanabe

Citations: 6 • 2017

2400-MFLOPS reconfigurable parallel VLSI processor for robot control

Yoshichika Fujioka, Michitaka Kameyama

Citations: 6 • 2002

Parameterizable CORDIC-Based Floating-Point Library Operations

Nikhil Dhume, Ramakrishnan Srinivasakannan

Citations: 5 • 2012

Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA

Citations: 5 • 2016

An efficient hardware design of SIFT algorithm using fault tolerant reversible logic

Chandrajit Pal, Pabitra Das, Sudhindu Bikash Mandal, Amlan Chakrabarti, Ranjan Ghosh

Citations: 5 • 2015