Shahedur Rahman
Papers
1
Total Citations
3
H-Index
1
About
Shahedur Rahman is a researcher in digital circuit design and optimization, with a focus on developing efficient arithmetic units for microprocessors. His most-cited work, "An FPGA-Based Divider Circuit Using Simulated Annealing Algorithm" (2018), addresses one of the most challenging operations in computing—division—by introducing a novel algorithm that leverages simulated annealing. Rahman proposed a heuristic function to navigate global and local optima, enabling faster and more resource-efficient division on FPGA platforms. This contribution stands out for its innovative application of metaheuristic optimization to hardware design, offering a practical solution to a long-standing bottleneck in microprocessor performance. With 3 citations, this paper has sparked interest among researchers exploring heuristic-driven digital architectures. Rahman’s work bridges the gap between algorithmic optimization and hardware implementation, demonstrating how techniques from artificial intelligence can enhance fundamental computing operations. His research is particularly valuable for students and engineers working on low-power, high-speed embedded systems, where efficient division circuits remain critical.
Research Focus
Key Achievements
Top Papers
- 1An FPGA-Based Divider Circuit Using Simulated Annealing Algorithm3 citations · 2018