K Ramananjaneyulu

About

K. Ramananjaneyulu is a researcher whose work centers on digital system design, particularly the FPGA implementation of processors and embedded systems. His most cited paper, "FPGA Implementation of a 64-Bit RISC Processor Using VHDL" (2012, 6 citations), introduces a 64-bit RISC processor with a built-in-self-test (BIST) feature, implemented using VHDL and verified on the Xilinx ISE simulator. This contribution is notable for its practical applicability across FPGA, System-On-Chip (SOC), and Spartan 3E platforms, offering a scalable solution for educational and prototyping environments. Ramananjaneyulu’s work demonstrates a strong focus on bridging hardware description languages with real-world verification, making his research valuable for students and engineers exploring processor architecture and digital logic design. While his citation count is modest, his paper serves as a foundational reference for those beginning work in FPGA-based RISC processors, reflecting his role in advancing accessible, testable digital systems. His achievements highlight the importance of integrating testing features directly into hardware designs, a key consideration in modern VLSI and embedded systems.

Research Focus

Key Achievements

Top Papers

1. 1
   FPGA Implementation of a 64-Bit RISC Processor Using VHDL

   6 citations · 2012

Key Collaborators

Contact & Links