Chaitali Chakrabarti

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About

Chaitali Chakrabarti is a leading figure in energy-efficient and high-performance VLSI design, with a core focus on architectures for signal processing, machine learning, and embedded systems. Her work has been instrumental in bridging the gap between algorithm development and hardware implementation, particularly for resource-constrained platforms. She has made major contributions to low-power design methodologies, including dynamic voltage scaling and adaptive architectures, and has pioneered techniques for efficient on-chip communication and memory management. Her research on hardware accelerators for deep learning and computer vision has been widely adopted, with her most-cited papers collectively garnering thousands of citations, reflecting their profound influence on both academic research and industrial practice. A notable recent achievement is her leadership in the "CLAIRE" project, which introduces composable chiplet libraries for scalable AI inference, addressing the critical challenge of post-Moore's Law computing. Her work on fault-tolerant architectures and biomedical signal processing further underscores her versatility. A Fellow of the IEEE, Chakrabarti’s research continues to shape the future of energy-aware computing, making her a pivotal mentor for students and researchers exploring the intersection of hardware and intelligent systems.