22.1 A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing

摘要

Emerging Artificial Intelligence-enabled Internet-of-Things (Al-loT) SoCs [1–4] for augmented reality, personalized healthcare and nano-robotics need to run a large variety of tasks within a power envelope of a few tens of mW: compute-intensive but bit-precision-tolerant Deep Neural Networks (DNNs), as well as signal processing and control requiring high-precision floating-point. Performance and energy constraints vary greatly between different applications and even within different stages of the same application. We present Marsellus (Fig. 22.1.1), an all-digital Al-loT end-node heterogeneous <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathsf{SoC}$</tex> fabricated in GlobalFoundries <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$22\mathsf{nm}$</tex> FDX that combines three key contributions to enable aggressive scaling of performance and energy: 1) a generalpurpose cluster of 16 RISC-V DSP cores attuned for execution of a diverse range of workloads exploiting <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\mathsf{b}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2\mathsf{b}$</tex> arithmetic extensions (XpulpNN), combined with fused MAC <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\&amp;$</tex> LOAD (M&L) operations and floating-point support; 2) a 2-8b reconfigurable binary engine to accelerate <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3\times 3$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1\times 1$</tex> (pointwise) convolutions in DNNs; 3) a set of On-Chip Monitoring (OCM) blocks connected to an Adaptive Body Bias (ABB) generator and a hardware control loop, enabling on-the-fly adaptation of transistor threshold voltages.