Single-precision floating-point format
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Analysis of effects of using exponent adders in IEEE-754 multiplier by VHDL
Ragini Parte, Jitendra Kumar Jain
Citations: 9 • 2015
Related papers: 1
Analysis of effects of using exponent adders in IEEE-754 multiplier by VHDL
Ragini Parte, Jitendra Kumar Jain
Citations: 9 • 2015