Self-Timed Circuit Synthesis and Its Verification

Abstract

The advantages of self-timed (ST) circuits compared to synchronous counterparts (extremely wide operability range in terms of supply voltage and ambient temperature, several times higher tolerance to soft errors, etc.) make them a promising basis for implementing naturally reliable digital circuits and robotic systems. However, the ST circuit design differs greatly from the synchronous circuit one in style and implementation features. The development of computer-aided design tools for ST circuits can facilitate and improve the efficiency of the ST unit design process. The paper proposes a logical synthesis design flow for the ST circuits. It complements a typical design flow for developing synchronous digital VLSI on base chips with specific stages inherent in the ST circuit synthesis: logical function dualization, an indication subcircuit generation, and self-timing analysis. In this case, the methods of converting the synchronous prototype description into an ST circuit and substituting templates of arithmetic and sequential units are used. The proposed design flow is implemented as an ST circuit logical synthesis subsystem. It is based on heuristic algorithms that theoretically guarantee the synthesis correctness. However, at the stage of debugging the synthesis subsystem, the results of its work need to be verified. The article describes the results of this verification on ST circuit examples with varying complexity. It proves the developed software tool's effectiveness for ST circuit synthesis, which guarantees the obtaining of a circuit with all the properties and advantages of ST circuits and consumer characteristics close to the manual synthesis results.