Design of Continuous-Time Sigma-Delta Modulator with Noise Reduction for Robotic Light Communication and Sensing

Abstract

The proposed continuous-time sigma-delta (ΣΔ) modulator employing nonreturn-to-zero (NRZ) digital-to-analog converter (DAC) and pulse shaping to achieve the performance of reducing the impact of clock jitter noise reduction is presented. The proposed modulator comprises a third order RC operational-amplifier-based loop filter, 4-bit internal quantizer operating at 160 MHz and three DACs. The NRZ DAC with quantizer excess loop delay compensation is set to be half the sampling period of the quantizer. The ΣΔ modulator dissipates 10.1 mW at 1.2 V supply voltage is implemented in the TSMC 0.18 um CMOS technology for robotic light communication and intelligent sensor fusion. Measured results illustrate that the ΣΔ modulator achieves 66.9 dB SNR, a peak 62 dB SNDR and 10.3 ENOB over a 10 MHz band at an over-sampling ratio (OSR) of 8. Including pads, the chip dimension is 0.363mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .