High-level synthesis for FPGA design based-SLAM application

Abstract

The development of SLAM algorithms in the era of autonomous navigation and the growing demand for autonomous robot in place of human being, has put into question how to reduce the computational complexity and make use of these algorithms to operate in real time. Our work aims to take advantage of the high level synthesis (HLS) on FPGAs to design a real time SLAM application. Precisely, we evaluate the promess-held by the new modern low power FPGAs in accelerating SLAM algorithms. Throughtout this, we will attempt to implement a well-known algorithms (FastSLAM2.0), on a new modern FPGA using OpenCL, a standard high level language. Our implementation results show a significant improvement of the algorithm processing time on an FPGA device over a modern powerful embedded GPGPU.