Zynq SoC-based IPs for Deep Learning Neural Networks

Abstract

Deep Learning Neural Networks (DLNNs) involve computationally intensive operations and are associated with a collection of interconnected artificial neurons. DLNNs can provide intelligent information systems that find a place in many areas from healthcare to robotics. High-speed and low-latency performance are important constraints of these networks. VGG-16 architecture used for object detection is based on the idea of Convolutional Neural Network (CNN) and applies the technique of deepening the network to extract the best use of CNNs. Its architecture consists of 16 layers making its training process extremely slow. It highly depends on multiplication and addition operations over the inputs and weights data. This introduces high computational complexity. This work aims to design an IP for the convolutional layer along with the Rectified Linear Activation Unit (ReLU) function and zero padding operation, a max pooling IP, and an IP for a low-latency implementation of the final fully connected layer with ReLU activation followed by softmax activation layer of VGG-16 architecture. High level hardware-based code-optimization methods for VGG-16 are presented to be accelerated in an FPGA based environment. Vitis HLS (High-Level Synthesis) tool was used to describe the proposed systems through a High-Level Language (HLL) C++ programming.