A Hardware Accelerator for Contour Tracing in Real-Time Imaging

Abstract

Contour tracing is a critical technique in image analysis and computer vision, with applications in medical imaging, big data analytics, machine learning, and robotics. We introduce a novel hardware accelerator based on the adapted and segmented (AnS) vertex following (VF) and run-data-based-following (RDBF) families of fast contour tracing algorithms implemented on the Zynq-7000 field-programmable gate array (FPGA) platform. Our algorithmic implementation utilizing a mesh-interconnected multiprocessor architecture is at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$55\times $ </tex-math></inline-formula> faster than the existing implementations. With input-output overheads, it is up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$12.5\times $ </tex-math></inline-formula> faster. Our hardware accelerator for contour tracing is benchmarked on mesh-interconnected hardware, all three families of contour tracing algorithms, and a random image from the Imagenet database. Our implementation is, thus, faster for FPGA, application-specific integrated circuit (ASIC), graphics processing unit (GPU), and supercomputer hardware in comparison to the central processing unit (CPU)–GPU collaborative approach and offers a better solution for those systems where the input-output overheads can be minimized, such as parallel processing arrays and mesh-connected sensor networks.