A FPGA-based Accelerator Implementation for Path Planning using Q_learning Algorithm

Abstract

Abstract As one of the most classic reinforcement learning, Q_learning has a very wide range of applications in the control filed of robot. Path planning which is the center of robot control has high computation speed requirements for algorithms, so we need to accelerate by hardware while planning path using Q_learning. In this paper, a hardware accelerator architecture based on FPGA is implemented to accelerate Q_learning while used in path planning. And we evaluate our design on Artix-7 DDR3 board, leading to less FPGA resource consumption and swifter computation speed. Comparing to Q_learning which implemented based on CPU, the speed has improved approximately 519 times, achieving the purpose of accelerating the Q_learning algorithm.