A hardware architecture of face detection for human-robot interaction and its implementation

Abstract

This paper presents hardware architecture with low-complexity face detection (FD) and parallel processing of local binary pattern (LBP) generation and adaptive boosting (AdaBoost) algorithm using Haar features for the intelligent service robot system. We designed a fully pipelined architecture implemented with the design techniques, such as variable image scaling and parallel processing multiple classifiers without integral image generation, on the FPGA platform. The proposed architecture enables a real-time FD processing for a VGA video at 30 frames per second.