Fully pipelined CORDIC‐based inverse kinematic FPGA design for biped robots

Abstract

A high‐speed field‐programmable gate array (FPGA) design is proposed to calculate angles and distances for biped robots in real time. A low‐complexity and high‐accuracy hardware‐oriented algorithm based on CORDIC was developed. To reduce hardware cost, a hardware sharing technique was used to realise a CORDIC scaling factor generator and three hardware sharing machines. Moreover, the multipliers and dividers were replaced by cost‐efficiency components, such as adders and shifters to further reduce hardware cost. In addition, the proposed design was implemented with a fully pipelined architecture, which achieved improved operating frequency and throughput efficiency. The proposed design was realised and verified by an FPGA device with a maximum operating frequency of 127 MHz, which achieved the calculation of angles and distances for biped robots in real time. Compared with the previous design, this work not only reduced hardware cost by at least 49.6% and average errors by at least 67.2%, but also improved the average executing performance by 62.7% when calculating ten angles for the biped robots.