A Proposal for Yield Improvement with Power Tradeoffs in CMOS LNAs (English Version)

Abstract

This paper studies an architecture with digitally controllable gain and power consumption to mitigate the impact of process variations on CMOS low-noise amplifiers (LNAs). A \SI{130}{nm}, \SI{1.2}{V} LNA implementing the proposed architecture is designed based on an analysis of variability in traditional LNAs under different bias currents and on the corresponding effects on the performance of a complete receiver. Two different adjustment strategies are evaluated, both of which are compatible with previously reported built-in self-test (BIST) circuits. Results show that the proposed architecture enables yield enhancement while keeping low-power operation compared with traditional LNAs.