Impact of Passive Element Technological Limits on CMOS Low-Noise Amplifier Design

Abstract

This paper investigates the impact of technological constraints on passive elements in the design of inductively degenerated CMOS low-noise amplifiers (LNAs). A theoretical analysis is combined with circuit simulations in a 130-nm CMOS process at 2.45~GHz to explore how the available inductance and capacitance values limit key design objectives such as maximum gain, minimum power consumption, and transistor sizing. Results show that these limits significantly restrict the achievable design space, particularly for low-power implementations, and highlight the need to incorporate detailed passive-element models into RF integrated circuit design flows.