The Comparative Analysis of the Maximum Slew Rate of the Output Voltage BJT and CMOS (SiGe TSMC 0.35µ) Operational Amplifiers

摘要

The authors compare two options for constructing operational amplifiers (Op-Amp) with a classical two-stage architecture on the maximum slew rate (SR) used in electronic devices of automatics (EDA) and robotics when implemented in the framework of BJT and CMOS technologies. The analysis is carried out for the case when the transfer function of the Op-Amp open-loop gain is described by the first-order lag. It is established that for typical Op-Amps on bipolar transistors the SR doesn't practically change over a wide range of static currents of the standard input differential stage (DS), which (in most cases) performs the role of the correction capacitance driver DCc (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ). It is shown that the CMOS Op-Amps have substantially comprehensive facilities, in which the SR can exceed the SR of similar BJT Op-Amps by several tens of times. However, when the input stages of the compared BJT and CMOS Op-Amps operate in microregime, their high-speed response (at identical unity gain frequencies) is approximately the same. A comparative analysis of two formulas used in the theory of the EDA for the estimation of SR, which enables to determine the limits to their applicability and clarify the recommendations for constructing the high-speed Op-Amps for hardware tasks of robotic and mechatronic systems.