Digital Hardware Implementation of Optimized Spiking Neurons

摘要

Neuromorphic computing and spiking neural networks have seen growing attention lately, especially in combination with event-based sensors and in robotics. To deploy such spiking neural networks, suitable hardware platforms are required. Neuromorphic hardware can be built based on various neuron models. However, only few publications so far investigate which neuron models are best suited for hardware implementation and many platforms use simple models like leaky integrate-and-fire. This work investigates how various neuron models can be implemented in hardware, applying different optimization and approximation techniques. The optimized neurons are prototyped on a field-programmable gate array and compared based on hardware resource requirements, power consumption and accuracy versus non-optimized models. Promising candidates for hardware implementation are pointed out and different metrics are evaluated, providing a guideline to trade-off the hardware implementation and performance for different neuron types.