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Design of robust-fault-tolerant arithmetic circuits and their application

Takeshi Kasuga, Michitaka Kameyama, T. Kiguchi

Year
2002
Citations
2

Abstract

Robust-fault-tolerant arithmetic circuits for a highly safe digital system are proposed. Two kinds of robust-fault-tolerant arithmetic circuits based on distributed coding are designed. One is a robust-fault-tolerant adder, and the other is a robust-fault-tolerant multiplier. It is shown in an experiment of robot control that the safety of the proposed arithmetic circuits is superior to that of the ordinary binary arithmetic circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Keywords

Fault toleranceAdderComputer scienceArithmeticElectronic circuitRobustness (evolution)Multiplier (economics)Coding (social sciences)Binary numberDigital electronics

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