<title>Focal-plane VLSI processing for multiresolution edge extraction</title>

Abstract

The challenge of information extraction in robot vision and automated inspection requires the development of efficient and dedicated hardware systems. A specific requirement relates to the hierarchical description of a scene, which is difficult to implement in real-time on conventional computers. Hardware solutions may exploit parallel computing capabilities in order to provide intelligent sensing of visual information. A promising strategy seeks to exploit VLSI solutions in novel architectures for optical sensing and processing. The Multi- port Array photo-Receptor system (MAR) discussed in this paper combines optical transduction with integrated focal-plane processing. The central element of the MAR system is a full custom VLSI photo-sensor array with hexagonal tessellation which provides parallel analog read-out from groups of pixels over prescribed areas. The overall capability of the sensor is enhanced by the addition of external analog computation which performs real-time spatial convolution at multiple resolutions and uses feedback control for automatic edge tracking. Current VLSI technology allows the fabrication of a CMOS sensor array with dimensions of up to 500 X 500 pixels on a 1.5 cm die using CMOS 1.2 micron technology. VLSI also provides means to integrate analog computing modules and microcontrol capabilities. A set of chips required by the system has been fabricated and a first prototype which integrates an array of 128 X 128 pixels with zero-crossing detection at seven different spatial resolutions runs at a rate of 1 M pixel/sec. Edge data at multiple resolutions are computed in real-time. Parallel edge extraction at 16 different resolutions will be available from a forthcoming unit. The sensor includes arbitrary pixel displacement and non-linear dark current compensation. This type of integrated sensor is a good candidate for advanced applications which require small weight and size.