A parallel neural network emulator based on application-specific VLSI communication chips

Abstract

This work describes a parallel neural network emulator which combines use of application-specific VLSI communication processors and standard DSPs as programmable processing elements. Locally interconnected communication processors attached to each DSP can span up to 2D- or 3D-grids containing large number of computing nodes and thus form highly parallel multiprocessor networks capable of global pipelined packet switched routing. The use of standard DSPs as processing elements enables the emulation of different types of neurons. These include biologically inspired models with learnable synaptic weights and delays, variable neuron gain, and static and dynamic thresholding. We describe applications of the emulator that include neural robot control as well as temporal signal processing, e.g. beamforming.