FPGA-based floating-point UD filter coprocessor for integrated navigation systems

Abstract

The Kalman filter plays an essential role in an integrated navigation system. From an embedded-system design point of view, the UD filter is a convenient, numerically-stable version of the Kalman filter. In this paper, a UD filter coprocessor with single-precision floating-point format that runs in FPGA is presented. A comprehensive hardware/software exploration is carried out in order to find the combination of subsystems that achieves the best throughput. Such examination determines that the best solution is fully in hardware. In addition, it is demonstrated the convenience of using high-level development tools to synthesize in hardware algorithms that have been originally designed to run on a general purpose microprocessor. Then, a UD filter for a 21-states system is developed as a coprocessor for system-on-chip integration. The coprocessor is validated using real-world data sets. Measurements of area, power, and energy are provided. It is found that the coprocessor is suitable for mid-range FPGA. In conclusion, it is demonstrated that new hybrid FPGA are adequate devices to implement battery-operated navigation systems for robotics.