Energy efficient VLSI circuits for machine learning on-chip

Abstract

The machine-learning based data analytics to support a cloud intelligence (such as Google's αGo) has already gone beyond the scalability of the present computing technology and architecture. The current deep learning based method is not efficient and requires huge consumption of data and power, which has a long latency running on data servers. With the emergence of autonomous vehicles, unmanned aerial vehicles and robotics, there is a huge demand to only analyze a necessary sensed data with small latency and low power at edge devices. In this talk, we will discuss efficient machine-learning algorithms such as fast least-squares method, binary and tensory convolutional neural network method, with according prototyping accelerator developed in FPGA and CMOS-ASIC chips, which has potential to outperform traditional GPU devices. The mapping on future RRAM device will be also briefly addressed.