Simulation and Performance Evaluation of Network on Chip Architectures and Algorithms using CINSIM

Abstract

The continuous saturation problems of today’s buses introduced due to large number of resources has lead the System on Chip (SoC) designers to research a new SoC paradigm known as Networks-on-Chip (NoC). The research related to NoC is still in its infancy and researchers are trying to propose, design and explore different architectures, algorithms and simulation tools related to NoC. In this paper we have explored a tool named as CINSIM (Component Based Interconnection Network Simulator) that is designed for linux systems by a research team at Real-Time Systems and Robotics of Technische Universitat Berlin. First we introduced the simulation components and environment related to the tool and then applied the tool on a heterogeneous 2D-Mesh Network on Chip architecture. We showed how the different combinations of routing algorithms, switching techniques, simulation types, traffic sources and measurement types can be used to check the performance evaluation of the underline heterogeneous NoC which in turn shows the general methodology of simulation and performance evaluation of any NoC platform under consideration. We hope this effort will help many NoC researchers for the quick design, analysis and selection of particular NoC platforms.