High-speed 2-D hardware convolution architecture based on VLSI systolic arrays

Abstract

The design of a special-purpose systolic image convolution processor for use in a robot vision system is described. It presents a high-speed two-dimensional hardware convolution architecture based on VSLI systolic arrays for image processing applications. An architecture for the parallel processing of the generalized two-dimensional convolution is summarized. A VLSI convolution chip was designed to accommodate various convolution window sizes. The number of coefficients being handled is directly proportional to the number of systolic computing elements (processors) used. In the present design three such processors are configured on one VLSI chip. Signed coefficients and unsigned data of eight bits are supported. All processing and interprocessor communications are performed bit-serially. The chip design incorporates error detection during convolution, and overflow avoidance techniques are possible for maximum system autonomy. The chip is estimated to operate at a maximum frequency of 16 MHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>