A reconfigurable spiking neural network digital ASIC simulation and implementation

Abstract

A reconfigurable spiking neural network is implemented in a 0.5 ¿m CMOS digital tiny-chip. The connection weights are uploaded to registers on the ASIC. These weights are learned off-line, using combined simulated annealing and genetic algorithm. Large computational power and many simulations create small powerful networks that are adapted to interact with the environment. These configurations are swapped in and out of the ASIC to cope with varying situations and increase robustness. The network has been successfully tested with a simulated robot in a maze and can be extended for target recognition.