A programmable real-time systolic processor architecture for image morphological operations, binary template matching and min/max filtering

Abstract

Mathematical morphology, min/max, and binary template matching operations can form a sufficiently complete image analysis system for a broad range of industrial/robotics applications. The authors present a bit-level systolic pipeline architecture for performing these operations in real time. The architecture is obtained by mapping algorithms to array structures, and it is flexible with respect to kernel sizes and processing stages. The architecture is best suited for high clock frequency and will have easy and low-cost implementation with FPGAs (standard chips) or custom ASICs (application-specific integrated circuits).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>