A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications

Abstract

SH ISA patents were filed in 1991 by Hitachi, and expired in 2014. Thereafter the ISA belonged to the public domain. We developed a 2-stage pipeline SH-2 CPU core, which expends only 4,655 logic cells of Intel MAX 10 FPGA fabricated on 55nm embedded NOR flash technology, 33KG of 40nm NVM process at 240MHz, and 20KG of 0.18um process at 80MHz. We bifurcated the RTL to (1) SoC integration, and (2) small FPGA, each optimized for the respective technology. The MCU which incorporates the CPU supports AHB, APB, UART, CAN-FD, PWM, and ADC. We plan to move this solution to IoT, edge AI and robotic applications. GNU and other compilers, assemblers, simulators, debuggers support the CPU.