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General-purpose vision chip architecture for real-time machine vision

Takashi Komuro, Idaku Ish, Masatoshi Ishikawa

Year
1997
Citations
10

Abstract

To solve the I/O bottleneck problem in existing vision systems and to realize versatile processing adaptive to various and changing environments, we propose a new vision chip architecture for applications such as robot vision. The chip has general-purpose processing elements (PEs) with each PE being directly connected to a photo detector (PD) and can implement various visual processing algorithms. We developed and simulated some sample programs for the chip and proved that they can be processed within 1 ms/frame, a rate that is high enough for high-speed visual feedback for robot control. Aiming to complete the chip, we are now developing test chips based on the architecture. The latest design has 8 x 8 PEs and PDs in an area 3.3 mm x 3.0 mm using a 0.8 μm CMOS process.

Keywords

BottleneckFrame rateComputer scienceChipMachine visionFrame (networking)Process (computing)Image processingArtificial intelligenceArchitecture

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