1. Executive Overview {#executive-overview}

Mythic is a semiconductor company developing Analog Processing Units (APUs) built around a proprietary analog compute-in-memory architecture. Its flagship silicon, the M1076 Analog Matrix Processor (AMP), delivers up to 25 TOPS at a typical power envelope of 3–4 watts — a power-efficiency profile the company positions as desktop-GPU-level compute at roughly one-tenth the power consumption. The core technical insight, developed by co-founder Laura Fick as part of her PhD thesis at the University of Michigan, is that storing neural-network weights directly in on-chip flash memory and performing matrix multiplication in the analog domain can eliminate the external DRAM bottleneck that dominates the energy budget of conventional digital inference accelerators. The company's leadership bench is credentialed: CEO Taner Ozcelik founded NVIDIA's automotive division and built it to a multi-hundred-million-dollar business; CTO and co-founder Dave Fick holds a PhD in Computer Science & Engineering from Michigan; and VP of NVM Technology Hùng Q Nguyễn brings over 100 patents and prior startup experience scaling ventures to multi-hundred-million-dollar revenue.

The company has attracted meaningful institutional capital. DCVC covered a $125M fundraise tied to "breaking through AI's power wall" (reported December 2025 on dcvc.com), and an earlier EE Times report documented an investor rescue that brought the current leadership team into place. These data points together sketch a company that has navigated a significant transition and is now executing under a reconstituted executive structure. The geographic footprint includes an India engineering center headed by Manoj Kumar (VP of Mythic India), signaling that the engineering organization has scaled internationally.

Not yet disclosed publicly: precise founding date, headquarters location, total headcount, or cumulative revenue. Mythic is invited to claim or correct any of these details.

2. The Company Story {#the-company-story}

Mythic's origin is academic. Co-founder Laura Fick developed the analog compute-in-memory technology that underpins every Mythic product as part of her doctoral research at the University of Michigan. Co-founder and CTO Dave Fick, also a Michigan PhD, joined her in translating that research into commercial silicon. The founding proposition was specific: as neural networks grew larger, the energy cost of repeatedly shuttling weight parameters between off-chip DRAM and compute units was becoming the dominant bottleneck for edge inference. Mythic's answer was to store weights permanently in on-chip flash and compute in the analog domain — eliminating the memory-bandwidth tax entirely.

VP of NVM Technology Hùng Q Nguyễn joined Mythic in January 2017, which provides the earliest publicly available personnel timestamp and establishes that the company was active by at least that date. The EE Times coverage of an "investor rescue" and a subsequent leadership transition brought Taner Ozcelik in as CEO. Ozcelik's background is explicitly in commercialization at scale: he built NVIDIA's automotive business, led the Intelligent Sensing Group at ON Semiconductor, and served as EVP & GM at Luminar Technologies. His hiring signals a deliberate pivot from research-and-development mode toward product-market execution.

A notable structural element is the integration of videantis, whose CEO Hans-Joachim Stolberg now sits on the Mythic team page. Videantis's platform is described as powering ADAS and IVI systems across more than 20 million vehicles, with customers including Bosch, Continental, Valeo, and Ficosa. The precise nature of the videantis–Mythic relationship (acquisition, partnership, or personnel hire) is not disclosed in the available data. Our read: the presence of Stolberg and the automotive pedigree of multiple team members suggests Mythic is actively cultivating the automotive and industrial AI markets as commercial targets, though this has not been stated as formal company strategy.

3. Product Portfolio {#product-portfolio}

Products & versions

C30

DELIVERY

DINERBOT T9 Pro

HOSPITALITY

KLEENBOT C30

CLEANING

BUTLERBOT W3

DELIVERY

DINERBOT T9

DELIVERY

T10

HOSPITALITY$15,000

Mythic's commercial product lineup is organized around a single core silicon — the M1076 Analog Matrix Processor — and two M.2 evaluation/deployment cards that carry it.

The M1076 AMP is the foundational chip: a 19mm × 15.5mm BGA package integrating 76 AMP tiles with Mythic's proprietary ACE™ (Analog Compute Engine) technology, delivering up to 25 TOPS at 3–4W typical power. It stores up to 80 million weight parameters on-chip, supports INT4 and INT8 operations, and connects via a 4-lane PCIe 2.1 interface providing up to 2 GB/s bandwidth. Peripheral interfaces include I²C, QSPI, UART, and 10 GPIO pins — a breadth appropriate for embedded and edge deployments. The chip is pre-qualified for practical computer-vision workloads including YOLOv3 (object detection), ResNet-50 (classification), and OpenPose (pose estimation).

The two M.2 cards make the M1076 accessible as a plug-in module. The ME1076 is an A+E key card (22mm × 30mm) with a 2-lane PCIe 2.1 connection delivering up to 1 GB/s, suited for compact edge devices. The MM1076 is an M-key card (22mm × 80mm) with a 4-lane connection at up to 2 GB/s, targeting more bandwidth-demanding applications such as video surveillance and industrial machine vision. Both cards eliminate external DRAM, support Ubuntu, NVIDIA L4T, and Windows (future), and are compatible with PyTorch, TensorFlow 2.0, and Caffe. The framework compatibility ensures that customers working in standard ML toolchains can deploy trained models without rebuilding their development pipeline.

The portfolio is currently focused on a single inference-acceleration use case at the edge. It does not, based on available data, include a training chip, a cloud accelerator, or a discrete software-only product.

4. Technology Stack {#technology-stack}

The M1076's defining architectural choice is analog compute-in-memory using flash as the storage medium. Conventional digital inference accelerators separate memory (DRAM) from compute (digital MAC arrays); the energy cost of crossing that boundary at high frequency is substantial. Mythic's approach, as described in its own product materials, performs matrix multiplication directly within the memory array in the analog domain — weights stored as analog conductance values in flash cells are multiplied by input voltages, and the resulting currents are summed on the wire, implementing a dot product without ever moving weight data off-chip.

Our read: this architecture has well-understood tradeoffs. The power and area advantages are real — 3–4W for 25 TOPS is a competitive figure for a single chip at this weight capacity. The use of flash (a non-volatile memory) means weights are retained without power, enabling fast wake-from-idle, which matters for always-on edge inference. The support for INT4 and INT8 (but not, from available data, FP16 or BF16) suggests the chip is optimized for inference-only workloads on quantized models, which aligns with the pre-qualified network list (YOLOv3, ResNet-50, OpenPose are all standard quantizable architectures). The 76-tile AMP structure and the ACE™ branding indicate a tiled, scalable internal organization, though the details of inter-tile interconnect and on-chip digital post-processing are not publicly documented.

The software interface layer — supporting PyTorch, TensorFlow 2.0, and Caffe via what is presumably a compilation/mapping toolchain — is a necessary component for any inference accelerator, but Mythic has not publicly detailed the compiler stack, model coverage breadth, or operator support list beyond the three pre-qualified networks. Our read: the software stack is likely a significant ongoing engineering investment and a key factor in customer adoption friction. Chris Cubiss (VP of Software Engineering, 25+ years of industry experience at ON Semiconductor, Lattice, and LSI Logic) leads this effort.

Not yet disclosed: process node, foundry partner, analog-to-digital converter architecture, compiler/SDK documentation, or benchmark comparisons on standardized inference suites (e.g., MLPerf). Mythic is invited to share additional technical documentation.

5. Research, Papers, Authors, Labs {#research-papers}

Mythic is a commercial semiconductor product company, not a research-publishing organization. Its technical contributions to the field — particularly Laura Fick's foundational analog compute-in-memory PhD work at the University of Michigan — originate from academic research that predates or parallels the company's commercial phase. No peer-reviewed publications, preprints, or technical reports published under the Mythic corporate banner are referenced in the available data. This is consistent with the norms of the fabless semiconductor industry, where core IP is typically protected through patents rather than open publication. Hùng Q Nguyễn alone holds over 100 patents, reflecting the team's preference for IP protection over academic disclosure.

6. Media Evidence {#media-evidence}

Three external press touchpoints are confirmed in the available data. DCVC (dcvc.com) published a profile of Mythic in January 2022, providing early institutional-investor validation. DCVC published a second piece in December 2025 reporting that Mythic raised $125M specifically framed around breaking through "AI's power wall" — a direct endorsement of the company's core efficiency thesis. EE Times (eetimes.com), an authoritative semiconductor trade publication, covered a leadership transition event described as an "investor rescue" in which Dave Fick became CEO (prior to Taner Ozcelik's appointment). The EE Times piece is notable because trade coverage of leadership transitions typically reflects a period of significant corporate restructuring, lending credibility to the narrative of a company that has undergone a meaningful strategic reset.

7. Commercial Reality {#commercial-reality}

Revenue, customer counts, deployment volumes, and ROI metrics are not disclosed in any available public data. The product lineup — two M.2 evaluation/deployment cards and a discrete BGA chip with pre-qualified networks — is consistent with a company that has reached the commercial sampling or early-production stage, but no customer names, design wins, or unit shipment figures have been published. The $125M fundraise reported by DCVC in December 2025 indicates that the company retains investor confidence and has operational runway, but fundraising is not a revenue proxy.

Mythic is invited to disclose customer deployments, production volumes, design-win announcements, or any independently verified commercial metrics. Such disclosures would materially strengthen the commercial section of this report.

8. Markets and Use Cases {#markets-use-cases}

Mythic's product descriptions explicitly name video surveillance, industrial machine vision, and edge servers as target deployment environments. The pre-qualified network list — YOLOv3 for object detection, ResNet-50 for image classification, and OpenPose for human pose estimation — defines a practical application envelope: counting and identifying objects or people in camera feeds, classifying visual inputs in real time, and tracking human body positions. These are workloads with immediate commercial demand in physical security, manufacturing quality control, retail analytics, and smart-building management.

The automotive signal is stronger at the team level than the product level. Hans-Joachim Stolberg's videantis platform has been deployed in ADAS and IVI systems across 20 million vehicles by Tier-1 suppliers including Bosch, Continental, Valeo, and Ficosa. Taner Ozcelik built NVIDIA's automotive division. Vladi Korobov led imaging technology at ONSEMI with dominant positions in automotive sensors. Our read: the concentration of automotive domain expertise in the leadership team suggests automotive edge inference is either an existing or strongly anticipated market for the M1076 architecture, though no automotive design wins are confirmed in the available data.

The elimination of external DRAM is particularly relevant in always-on embedded and IoT contexts where both power budgets and PCB real estate are constrained. The 3–4W power figure and the sub-30mm M.2 A+E form factor speak directly to this class of deployment. Industrial robotics, smart cameras, and edge AI appliances are all plausible use-case extensions consistent with the product specifications.

9. Competitive Landscape {#competitive-landscape}

The market for edge AI inference accelerators is active, with multiple companies pursuing the power-efficiency problem through different architectural approaches — digital systolic arrays, near-memory digital compute, neuromorphic designs, and, as in Mythic's case, analog compute-in-memory. Mythic's differentiation rests on its flash-based analog architecture and the resulting elimination of off-chip DRAM, rather than on process-node leadership or raw peak-TOPS figures. Whether this architectural bet commands a durable moat or becomes one of several viable solutions depends on factors including software ecosystem maturity, production scale economics, and the evolution of quantization standards.

Our read: the company's competitive position is best assessed on power-per-TOPS-per-dollar at the system level (including the DRAM savings), not on chip-level TOPS alone. The module above provides the current peer set for context.

10. Country Advantage / Geopolitical {#geopolitical}

Section not material for this company.

11. Hype vs Real vs Ugly {#hype-real-ugly}

Verified and specific (grounded in product data):

• The M1076 delivers up to 25 TOPS at 3–4W in a 19mm × 15.5mm BGA package — these are published product specifications (company-claim).
• The chip stores up to 80 million weight parameters on-chip with no external DRAM required — company-claim, architecturally plausible and consistent with the analog compute-in-memory approach.
• The M.2 cards support YOLOv3, ResNet-50, and OpenPose — company-claim, these are real and widely used network architectures.
• The $125M fundraise was reported by DCVC, an independent third party — external validation.

Company claims requiring independent verification:

• "Desktop GPU-level AI compute at up to 1/10th the power" — company-claim. The comparison methodology, reference GPU, workload, and measurement conditions are not specified. The directional claim is architecturally plausible but cannot be independently verified from available data.
• "Up to 25 TOPS" — company-claim. Peak figures in chip marketing typically reflect best-case utilization. Real-world TOPS on practical networks may differ; no MLPerf or equivalent benchmark data is available.

Fixable gaps:

• Not yet disclosed: production availability status, foundry/process node, compiler SDK documentation, customer deployments, and any third-party benchmark results. Mythic is invited to provide these details for inclusion in a subsequent revision.

Our read: The core technology claim — that analog compute-in-memory using flash can deliver competitive inference performance at dramatically lower power — is scientifically grounded, having originated in peer-reviewed doctoral research. The commercial execution question (software maturity, yield, customer adoption) remains the open variable.

12. Future Scenarios {#future-scenarios}

Bull case — Our read: The analog compute-in-memory architecture proves durable as a differentiator at the edge, particularly in automotive and industrial applications where the power-envelope constraint is non-negotiable. The videantis integration and the team's Tier-1 automotive relationships yield design wins with major OEMs or system integrators. The $125M raise provides sufficient runway to reach production scale and build a software ecosystem that reduces customer integration friction. Mythic becomes a meaningful independent fabless semiconductor company in the edge-AI accelerator space.

Base case — Our read: Mythic secures a set of design wins in industrial machine vision and smart camera applications, where the M.2 form factor and pre-qualified networks lower the integration barrier. Revenue grows, but the automotive market proves to have a longer qualification cycle than anticipated. The company remains a specialized niche player, well-regarded technically, with a product that serves specific power-constrained use cases without displacing digital accelerators in higher-compute applications. A next-generation chip with expanded weight capacity or improved network coverage is required to grow the addressable market.

Bear case — Our read: The software ecosystem — compiler maturity, operator coverage, and toolchain integration — proves to be a sustained bottleneck that slows customer adoption. Digital accelerator competitors close the power-efficiency gap through process-node advances or near-memory compute. The analog approach's sensitivity to manufacturing variation creates yield or reliability challenges at production volume. The company is acquired, merges, or narrows its scope significantly. The EE Times "investor rescue" history is a reminder that this scenario has been proximate before.

13. What to Watch {#what-to-watch}

• Design-win announcements: Any named customer deployment — particularly in automotive, industrial, or surveillance — would be the single most important commercial signal.
• Next-generation silicon: A successor to the M1076 (higher TOPS, larger weight capacity, advanced process node) would indicate the roadmap is executing and the architecture is scaling.
• Software SDK release or documentation: Public availability of the compiler toolchain, operator support matrix, and developer documentation would signal readiness for broader ecosystem adoption.
• Automotive qualification progress: Given the team's concentration of ADAS expertise, any announced engagement with Tier-1 automotive suppliers (echoing the videantis/Bosch/Continental relationships) would validate the implied market thesis.
• MLPerf or equivalent benchmark submission: An independently verified inference benchmark result would provide the first apples-to-apples power-efficiency comparison.
• videantis relationship clarification: The precise structure of the Mythic–videantis relationship (acquisition, partnership, or team integration) has material implications for IP, revenue, and market access.
• Headcount and India center growth: Manoj Kumar's Mythic India operation is an indicator of engineering scale; growth signals active product development.

14. Sources & Methodology {#sources-methodology}

Primary source: All factual claims in this report are grounded exclusively in data extracted from Mythic's own website (mythic.ai), including the company About page, product specification pages, and team bios. All such claims are marked company-claim and should be understood as self-reported. They have not been independently audited.

Third-party press: Three external sources are cited — DCVC (dcvc.com, two articles: January 2022 and December 2025) and EE Times (eetimes.com, one article on the leadership transition). These are treated as independent validation of the specific facts they report (fundraise amount and framing; leadership change event), not as endorsements of product performance claims.

Inferences: Statements labeled "Our read:" are analyst inferences derived from the pattern of available facts. They are not company claims and have not been confirmed by Mythic.

Gaps: Where data is absent, this report uses the formulation "Not yet disclosed" and invites Mythic to provide corrections or additions. No figures, customers, competitors, partnerships, or specifications have been invented or extrapolated beyond what the source data supports.

Rubric (applied uniformly to every company assessed on this platform): Verified facts → stated plainly. Company claims → labeled as such. Analyst inferences → labeled "Our read:". Absent data → "Not yet disclosed" + invite to claim. Negative characterizations → only as fixable gaps or labeled inferences, never as unsourced assertions.