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FPGA based hardware accelerator for KAZE feature extraction algorithm

Lester Kalms, Ahmed Elhossini, Ben Juurlink

发表年份
2016
引用次数
4

摘要

Processing and understanding of visual data has a significant importance in many applications such as robotics and vision aid devices. Extracting image features is one of the important tasks in computer vision. This paper focuses on KAZE features algorithm, due to its good performance. KAZE features is a multi-scale 2D feature detection and description algorithm. It describes 2D features in a non-linear scale space by means of non-linear diffusion filtering. In this paper, the algorithm was optimized for speed, memory usage and portability. The paper presents a hardware accelerator for the scale-space analysis part of the algorithm on FPGA. A high speed-up has been achieved by this accelerator by parallelizing several parts of the algorithm and reducing the memory bandwidth.

关键词

Computer scienceField-programmable gate arraySoftware portabilityFeature extractionHardware accelerationScale spaceArtificial intelligenceBandwidth (computing)Feature (linguistics)Computer hardware

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